Memory systems
HBM Catalog
Version-level comparison of high bandwidth memory generations used around GPUs, AI accelerators, and HPC packages.
How to read this table
HBM numbers are usually quoted per stack. Accelerator-level bandwidth depends on the number of stacks and the vendor's memory controller implementation.
HBM3E is a product evolution around the HBM3 family, so published limits vary by supplier and product generation.
| Metric | HBM | HBM2 | HBM2E | HBM3 | HBM3E | HBM4 | HBM4E |
|---|---|---|---|---|---|---|---|
| Bus Width (Interface) | 1024-bit | 1024-bit | 1024-bit | 1024-bit | 1024-bit | 2048-bit | 2048-bit |
| Pin Speed (Signaling) | 1 Gb/s per pin | 2 Gb/s per pin | 3.6 Gb/s per pin | 6.4 Gb/s per pin | 9.6 Gb/s per pin | 8 Gb/s per pin | 16 Gb/s per pin |
| Peak Bandwidth per Stack | 128 GB/s per stack | 256 GB/s per stack | 461 GB/s per stack | 819 GB/s per stack | 1.3 TB/s per stack | 2 TB/s to 3.3 TB/s | 4 TB/s |
| Capacity per stack | 16 GB | 16 GB | 36 GB | 64 GB | 64 GB | 64 GB | 64GB |
| Channels | na | 8 independent channels | 8 independent channels | 16 independent channels | 16 independent channels | 32 independent channels | 32 independent channels |
| Stack heights | 8-Hi | 8-Hi | 12-Hi | 16-Hi | 16-Hi | 16-Hi | 16-Hi |
| Used by | Prior generation AI accelerators and HPC GPUs | Prior generation AI accelerators and HPC GPUs | Prior generation AI accelerators and HPC GPUs | H100-class and MI300-class AI accelerators | H200, B200, MI325X, MI355X | Next-generation AI and HPC accelerators | Next-generation AI and HPC accelerators |
| Sources |