Memory systems
DDR Catalog
Comparison of DDR-family memory standards that define the external memory envelope for CPUs and many edge accelerators.
How to read this table
DDR bandwidth is often quoted per 64-bit channel. System bandwidth depends on memory channels, DIMM population, and supported speed bins.
Vendor overclocking profiles are not the same as JEDEC baseline speeds, so this table emphasizes standard and platform-level behavior.
| Metric | DDR3 | DDR4 | DDR5 | DDR5 MRDIMM |
|---|---|---|---|---|
| Standard data rates | DDR3-800 to DDR3-2133 | DDR4-1600 to DDR4-3200 | DDR5-3200 to DDR5-6400 baseline class; newer bins extend higher | Platform-dependent; Intel Xeon 6 platforms advertise MRDIMM uplift |
| Channel shape | 64-bit channel | 64-bit channel | Two independent 32-bit subchannels per DIMM | Multiplexed ranks behind DDR5 electrical interface |
| Nominal voltage | 1.5 V nominal; DDR3L at 1.35 V | 1.2 V nominal | 1.1 V nominal | DDR5 platform dependent |
| Per-channel bandwidth | Up to 17.1 GB/s at DDR3-2133 | Up to 25.6 GB/s at DDR4-3200 | Up to 51.2 GB/s per 64-bit channel at DDR5-6400 | Designed to increase effective bandwidth versus standard RDIMM |
| Platform era | Older servers and client systems | Xeon Scalable, EPYC Naples through Milan, many client systems | Current server and client CPU platforms | Bandwidth-oriented server CPU platforms |
| Notes | Useful historical baseline for bandwidth-per-channel scaling. | Mature server memory generation before DDR5 doubled bank-group pressure and channel subdivision. | Higher concurrency, on-DIMM PMIC, and stronger ECC/RAS features for server platforms. | Important for memory-bandwidth-bound CPU workloads, but should be tracked by platform and DIMM generation. |
| Sources |